

------------sram control----------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity My_sramctrl is
	port(
			clk			: in std_logic;
			SWT   		: in STD_logic;
			dinin		: in STD_logic_vector (11 downto 0);
			
			SRAM_ADDR 	: OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
			SRAM_WE_N 	: OUT STD_LOGIC;
			SRAM_OE_N 	: OUT STD_LOGIC;
			SRAM_CE_N 	: OUT STD_LOGIC;
			SRAM_UB_N 	: OUT STD_LOGIC;
			SRAM_LB_N 	: OUT STD_LOGIC;
			SRAM_DQ 	: INOUT STD_LOGIC_VECTOR(15 DOWNTO 0);
			
			adcounter	: in std_logic_vector (17 downto 0);
			adcount 	: out std_logic;
			adreset		: out std_logic;
			
			dlycounter	: in std_logic_vector (5 downto 0);
			dlycount 	: out std_logic;
			dlyreset	: out std_logic;
			
			Ur_reset 	: OUT std_logic;
			Ur_load 	: OUT std_logic;
			Ur_data_in	: OUT std_logic_vector (15 downto 0);
			Lr_reset 	: OUT std_logic;
			Lr_load 	: OUT std_logic;
			Lr_data_in	: OUT std_logic_vector (15 downto 0);
			
			UARTdata_in	: in std_logic_vector (7 downto 0);
			data_frame	: in std_logic;
			data_stored	: out std_logic
			);
end My_sramctrl;

architecture beh of My_sramctrl is

	TYPE STATETYPE IS (S0U, S0L, S1U, S1L, S_init_delay1, S_loop_delay1, S_loop_delay2);
	
	SIGNAL currstate, nextstate: statetype;
	constant sixtyone : std_logic_vector(5 downto 0) := "111101";
	constant number : std_logic_vector(11 downto 0) := "000000000100";
	constant dincon : std_logic_vector(11 downto 0) := "000000000100";
	constant ad_zero : std_logic_vector(17 downto 0) := "000000000000000000";
	constant ad_one : std_logic_vector(17 downto 0) := "000000000000000001";
	constant ad_middle : std_logic_vector(17 downto 0) := "000010010101111111";
	
	SIGNAL delay, read_address :std_logic_vector(17 downto 0);
begin
state: PROCESS (currstate, SWT, dinin, SRAM_DQ, adcounter, dlycounter)
		BEGIN
			CASE currstate IS
				WHEN S_init_delay1 =>
					Ur_data_in <= SRAM_DQ;
					Lr_data_in <= SRAM_DQ;
					SRAM_ADDR <= ad_middle;
					SRAM_WE_N <= '1';
					SRAM_OE_N <= '1';
					SRAM_CE_N <= '0';
					SRAM_UB_N <= '1';
					SRAM_LB_N <= '1';

					Ur_reset <= '0';
					Ur_load <= '0';
					Lr_reset <= '0';
					Lr_load <= '0';
					
					data_stored <= '0';
					nextstate <= S0U;
				
					delay <= ad_zero;
					read_address <= ad_zero;
				WHEN S0U =>
					Ur_data_in <= SRAM_DQ;
					Lr_data_in <= SRAM_DQ;
					
					SRAM_ADDR <= ad_zero;
					
					SRAM_WE_N <= '1';
					SRAM_OE_N <= '0';
					SRAM_CE_N <= '0';
					SRAM_UB_N <= '0';
					SRAM_LB_N <= '0';
					
					delay <= delay;
					read_address <= ad_zero;
					
					Ur_reset <= '0';
					Ur_load <= '1';
					Lr_reset <= '0';
					Lr_load <= '0';
					
					data_stored <= '0';
					
					nextstate <= S0L;
				WHEN S0L =>
					Ur_data_in <= SRAM_DQ;
					Lr_data_in <= SRAM_DQ;
					
					SRAM_ADDR <= ad_middle;
					
					SRAM_WE_N <= '1';
					SRAM_OE_N <= '0';
					SRAM_CE_N <= '0';
					SRAM_UB_N <= '0';
					SRAM_LB_N <= '0';
					
					read_address <= read_address + ad_one;
					delay <= ad_zero;
					
					Ur_reset <= '0';
					Ur_load <= '0';
					Lr_reset <= '0';
					Lr_load <= '1';
					
					data_stored <= '0';
					nextstate <= S_loop_delay1;
					
				WHEN S_loop_delay1 =>
					Ur_data_in <= SRAM_DQ;
					Lr_data_in <= SRAM_DQ;
					SRAM_ADDR <= ad_middle;
					SRAM_WE_N <= '1';
					SRAM_OE_N <= '1';
					SRAM_CE_N <= '0';
					SRAM_UB_N <= '1';
					SRAM_LB_N <= '1';
					Ur_reset <= '0';
					Ur_load <= '0';
					Lr_reset <= '0';
					Lr_load <= '0';
					
					read_address <= read_address;
					delay <= delay + ad_one;
					
					data_stored <= '0';
					nextstate <= S_loop_delay2;
					
				WHEN S_loop_delay2 =>
					Ur_data_in <= SRAM_DQ;
					Lr_data_in <= SRAM_DQ;
					SRAM_ADDR <= ad_middle;
					SRAM_WE_N <= '1';
					SRAM_OE_N <= '1';
					SRAM_CE_N <= '0';
					SRAM_UB_N <= '1';
					SRAM_LB_N <= '1';
					
					Ur_reset <= '0';
					Ur_load <= '0';
					Lr_reset <= '0';
					Lr_load <= '0';
					
					read_address <= read_address;
					delay <= delay + ad_one;
					
					data_stored <= '0';
--					if (dlycounter < number and data_frame = '1') then
--						nextstate <= S_store_frame1;
--					else
					if (dlycounter = sixtyone) then
						if (dinin = dincon) then
							nextstate <= S0U;
						else
							nextstate <= S1U;
						end if;
					else
						nextstate <= S_loop_delay1;
					End if;
--					end if;
				
				WHEN S1U =>
				
					Ur_data_in <= SRAM_DQ;
					Lr_data_in <= SRAM_DQ;
					
					SRAM_ADDR <= adcounter;
					
					SRAM_WE_N <= '1';
					SRAM_OE_N <= '0';
					SRAM_CE_N <= '0';
					SRAM_UB_N <= '0';
					SRAM_LB_N <= '0';
					
					read_address <= read_address;
					delay <= delay;
					
					Ur_reset <= '0';
					Ur_load <= '1';
					Lr_reset <= '0';
					Lr_load <= '0';
					
					data_stored <= '0';
					nextstate <= S1L;
					
				WHEN S1L =>
				
					Ur_data_in <= SRAM_DQ;
					Lr_data_in <= SRAM_DQ;
					
					SRAM_ADDR <= adcounter + ad_middle;
					
					SRAM_WE_N <= '1';
					SRAM_OE_N <= '0';
					SRAM_CE_N <= '0';
					SRAM_UB_N <= '0';
					SRAM_LB_N <= '0';
					
					read_address <= read_address + ad_one;
					delay <= ad_zero;
					
					Ur_reset <= '0';
					Ur_load <= '0';
					Lr_reset <= '0';
					Lr_load <= '1';
					
					data_stored <= '0';
					nextstate <= S_loop_delay1;
					
--				WHEN S_store_frame1 =>
--				
--					Ur_data_in <= SRAM_DQ;
--					Lr_data_in <= SRAM_DQ;
--					
--					SRAM_ADDR <= frame_counter;
--					
--					SRAM_WE_N <= '0';
--					SRAM_OE_N <= '1';
--					SRAM_CE_N <= '0';
--					SRAM_UB_N <= '1';
--					SRAM_LB_N <= '0';
--					
--					
--					Ur_reset <= '0';
--					Ur_load <= '0';
--					Lr_reset <= '0';
--					Lr_load <= '0';
--					
--					data_stored <= '0';
--					nextstate <= S_loop_delay2;
--					
					
				END CASE;
		END PROCESS state;
		
		
		Statereg: PROCESS (clk)
		BEGIN
			IF (clk = '1' and clk'event) THEN
				IF (SWT = '0') THEN
					currstate <= S_init_delay1;
				ELSE
					currstate <= nextstate;
				END IF;
			END IF;
		END PROCESS statereg;
					
			
end beh;
